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Please use this identifier to cite or link to this item: http://artemis-new.cslab.ece.ntua.gr:8080/jspui/handle/123456789/6526

Title: 3d Integrated Circuits Ir-drop Estimation: Characterization, Extraction & Synthesis
Authors: Αναγνωστός Δημήτριος
Supervisor: Σούντρης Δημήτριος
Keywords: 3d integration
tsv
power delivery networks
ir-drop
memory-on-processor
circuit characterization
benchmark synthesis
sram
Issue Date: 23-Nov-2012
Abstract: Three-dimensional circuit integration is a promising technology, able to ensure thecontinuation of Moore’s Law and the production of highly dense silicon systems. Performance andpower consumption metrics profit from the reduction of wire lengths in the die, while silicon yieldincreases as the total surface of the integrated circuit is reduced in favour of vertical manufacturing.Yet 3D technology is not mature enough to support massive production. Cost issues and the intrinsicproblems of heat dissipation and vertical interconnection reliability are combined with the lack ofavailable, 3D specific, design automation and verification tools from major software vendors. Onlyrecently, with the introduction of commercial 2.5D ICs, the industry has started to develop 3Doriented EDA tools to assist designers.This thesis describes specific details from the development of an IR-Drop estimation tool,for memory-on-processor systems, as part of a collaborative, six month project funded by IntegratedSystems Laboratory, EPFL. Reliable power delivery becomes an important issue when moving to3D topologies, since all currents have to traverse the stack of dies before reaching the real powernodes. This effect leads to voltage drops that may surpass the margins for reliable operation.Moreover, memory-on-processor systems are expected to be some of the first 3D circuits to hit themarket, offering unparalleled performance. At the same time though memory circuits suffer greatlyfrom reduced voltages, especially when in sleep mode.The target of this tool is to offer designers an early estimation of the cells which are moreprone to failure due to unexpected drops in power distribution. For that reason the tool utilizesmodels of devices and power delivery networks which are close to the actual physical design,resulting in fine-grained voltage distribution maps. The tool is also thermal-aware, meaning that itcaptures the effect of Joule heating on power delivery and adjusts all affected devices accordingly.In the beginning, aspects of the tool creation process are discussed, followed by apresentation of the simulated systems. Extensive results are presented for 3D memory topologies andtheir effect on IR-Drop of large systems is explored. The thesis concludes with summarizingcomments and some suggestions for future improvements of the tool.
Notes: 
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